4 research outputs found
High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion
The purpose of this thesis is the proposal and implementation of data conversion
open-loop architectures based on voltage-controlled oscillators (VCOs) built with
ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to
the newest complementary metal-oxide-semiconductor (CMOS) nodes.
The scaling of the design technologies into the nanometer range imposes the
reduction of the supply voltage towards small and power-efficient architectures,
leading to lower voltage overhead of the transistors. Additionally, phenomena
like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between
devices and PVT variations) make the design of classic structures for ADCs more
challenging. In recent years, time-encoded A/D conversion has gained relevant
popularity due to the possibility of being implemented with mostly digital structures.
Within this trend, VCOs designed with ring oscillator based topologies
have emerged as promising candidates for the conception of new digitization
techniques.
RO-based data converters show excellent scalability and sensitivity, apart from
some other desirable properties, such as inherent quantization noise shaping and
implicit anti-aliasing filtering. However, their nonlinearity and the limited time
delay achievable in a simple NOT gate drastically limits the resolution of the converter,
especially if we focus on wide-band A/D conversion. This thesis proposes
new ways to alleviate these issues.
Firstly, circuit-based techniques to compensate for the nonlinearity of the ring
oscillator are proposed and compared to equivalent state-of-the-art solutions.
The proposals are designed and simulated in a 65-nm CMOS node for open-loop
RO-based ADC architectures. One of the techniques is also validated experimentally
through a prototype. Secondly, new ways to artificially increase the effective
oscillation frequency are introduced and validated by simulations. Finally, new
approaches to shape the quantization noise and filter the output spectrum of a
RO-based ADC are proposed theoretically. In particular, a quadrature RO-based
band-pass ADC and a power-efficient Nyquist A/D converter are proposed and
validated by simulations.
All the techniques proposed in this work are especially devoted for highbandwidth
applications, such as Internet-of-Things (IoT) nodes or maximally
digital radio receivers. Nevertheless, their field of application is not restricted to
them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas
de conversión de datos basadas en osciladores en anillos, compatibles
con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación
más modernos donde las estructuras digitales se ven favorecidas.
La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción
de la tensión de alimentación para el desarrollo de arquitecturas pequeñas
y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión
para saturar transistores, lo que añadido a una ganancia cada vez menor
de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones
de proceso, tensión y temperatura han llevado a que sea cada vez más complejo
el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión
A/D basada en codificación temporal ha ganado gran popularidad dado
que permite la implementación de estructuras mayoritariamente digitales. Como
parte de esta evolución, los osciladores controlados por tensión diseñados con topologías
de oscilador en anillo han surgido como un candidato prometedor para
la concepción de nuevas técnicas de digitalización.
Los convertidores de datos basados en osciladores en anillo son extremadamente
sensibles (variación de frecuencia con respecto a la señal de entrada) así como
escalables, además de otras propiedades muy atractivas, como el conformado
espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su
respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta
NOT restringen la resolución del conversor, especialmente para conversión A/D
en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas
técnicas para aliviar este tipo de problemas.
En primer lugar, se proponen técnicas basadas en circuito para compensar el
efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones
equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología
CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas
presentadas es también validada experimentalmente a través de un prototipo.
En segundo lugar, se introducen y validan por simulación varias formas de incrementar
artificialmente la frecuencia de oscilación efectiva. Para finalizar, se
proponen teóricamente dos enfoques para configurar nuevas formas de conformación
del ruido de cuantificación y filtrado del espectro de salida de los datos
digitales. En particular, son propuestos y validados por simulación un ADC pasobanda
en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente
para aplicaciones de alto ancho de banda, tales como módulos para el Internet
de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar
de ello, son extrapolables también a otros campos como el de la instrumentación
biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí
High-Speed and Energy-Efficient Ring-Oscillator for Analog-to-Digital Conversion
The aim of this conference is to offer the possibility to present and discuss new research results on the area of integrated circuits and systems and all its fields of application. A major emphasis has been given in the technical program to emerging topics such as electronic systems for artificial intelligence, reliability of circuits and devices, unconventional computing, smart sensors and other relevant topics. The conference on Design of Circuits and Integrated Systems (DCIS) is an international meeting for researchers in the highly active fields of micro- and nano-electronic circuits and integrated systems. It provides an excellent forum to present and discuss works on the emerging challenges offered by technology, in the areas of modeling, design, implementation and test of devices, circuits and systems. The 35th edition will be organized by Universidad Politécnica de Madrid
Resolution Enhancement of VCO-based ADCs by Passive Interpolation and Phase Injection
Proceeding of: 2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS), 20-22 November 2019, Bilbao, SpainThis work describes a simple way to improve the resolution of low-pass voltage-controlled-oscillators based analog-to-digital converters (VCO-based ADCs) implemented with ring-oscillators. We propose to insert a passive resistive network into the differential delay cells of the oscillator to get additional interpolated phases. These interpolated phases are then injected to other similar oscillators. By increasing the number of phases coming from all the oscillators, the effective gain of the system is higher and enhances the resolution of the converter. To validate the idea, a prototype of an open-loop VCO-based ADC was built in VerilogA language with ring-oscillators designed with a 65-nm CMOS process. The results of transient simulations were compared to the results of a behavioral ideal model of the system built in MATLAB. As expected, the signal-to-noise ratio (SNR) was improved in concordance with the increase in the number of phases. Finally, it was checked that the proposed circuit used to extract and inject the interpolated phases did not penalize the total power consumption. The proposed circuit structure is particularly suitable for high-bandwidth applications, where the oversampling ratio (OSR) is strongly restricted and the gain is limited because of the oscillator non-linearity. Due to the highly digital nature of the VCO-based ADC structures, this solution may be of special interest to be implemented in new deep-submicron CMOS processes.This work was supported by the CICYT project TEC2017-82653-R, Spain.Publicad
Ring-oscillator with multiple transconductors for linear analog-to-digital conversion
This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mVpp, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.This research was funded by Project TEC2017-82653-R, Spain